Present high-speed requirements for personal computers and workstations have forced an increase in operating speed of computational large scale integrated (LSI) circuits, such as central processing units (CPUs) or digital signal processors (DSPs). When the operating speed and the instant clock frequency of an LSI circuit increases, the thermal dissipation of the LSI circuit also increases. Accordingly, the LSI circuit or the peripheral circuits may fail to perform normal operations due to such thermal dissipation. Therefore, providing a proper cooling technique for the thermal dissipation of the LSI circuit is an urgent problem in this field.
An example for cooling an LSI circuit is a ventilation cooling method that implements cooling fans. According to the ventilation cooling method, the cooling fans can be installed on the opposite side of the surface of the LSI circuit, for example, so that the cooling fans can blow the cold air on the surface of the LSI circuit. During the cooling process of the LSI circuit, the ambient air temperature of the LSI circuit is monitored, and the rotating speed of the cooling fan can be adjusted in accordance with the monitored temperature that adjusts the cooling speed.
FIGS. 1A and 1B are the circuit diagrams illustrating the driving circuit of an electric fan motor and the peripheral circuits in accordance with the present invention. In FIGS. 1A and 1B, the driving integrated circuits (ICs) 200 have the same configuration but the peripheral circuits of the driving ICs 200 are different.
A power-supply pin 9 (i.e. VCC pin) is connected to an input supply voltage VDD via a diode D1 to prevent reverse current. In addition, the VCC pin 9 is connected to a zener diode ZD1 used for overvoltage protection and a capacitor C2 used for signal smoothing. A ground pin 14 is connected to the ground (i.e. GND). An output pin of an H bridge circuit 212 is connected to an electric fan motor 6 via a pin 6 (i.e. OUT2) and a pin 8 (i.e. OUT1). In addition, the pin on the lower part of the H bridge circuit 212 is connected to a pin 7 (i.e. RNF). It is noted that the pin numerals are numbered for the sake of brevity, and is irrelevant to the layout of the pins. A control logic circuit 208 generates a pulse signal S1, and the pulse signal S1 is a pulse width modulated signal. A pre-driving circuit 210 switches the H bridge 212 according to the pulse signal S1.
The electric fan motor 6 is a brushless direct current (DC) electric motor. The driving IC 200 in combination with the peripheral circuit components are configured as a driving circuit for driving the electric fan motor 6 in PWM. A Hall sensor 8 is installed nearby the electric fan motor 6 for detecting the rotor position.
The Hall biasing circuit 204 generates a Hall bias voltage VHB, and the Hall bias voltage VHB is supplied to the Hall sensor 8 via a pin 3. Hall signals H− and H+ generated by the Hall sensor 8 are supplied to a pin 2 and the pin 3 of the driving IC 200 respectively. A Hall comparator 202 compares the Hall signals H− and H+, and generates a pulse signal S2 indicating the rotor position to a control logic circuit 208. The control logic circuit 208 and the pulse signal S2 are arranged to synchronously change the driving phases of the H bridge circuit 212.
A resistor RNF is connected between the H bridge circuit 212 and the ground line VSS. In other words, the resistor RNF is connected between pin 7 and a ground line. A detection voltage proportional to the current flowing to the electric fan motor 6 is generated across the resistor RNF. A detection voltage VNF is supplied to a pin 5 via a resistor-capacitor (RC) filter. A current clamping comparator 206 compares the detection voltage VNF with a specific voltage Vc1. The voltage Vc1 determines the upper bound current flowing through the electric fan motor 6. If the output of the current clamp comparator 206 is determined to be a high voltage level, the control logic circuit 208 changes the logic value of the pulse signal S1 to stop flowing current to the electric fan motor 6.
An oscillator 220 generates a periodic carrier voltage OSC having a specific frequency. The carrier voltage OSC has a sawtooth waveform or a triangle waveform. A PWM comparator 216 compares a voltage VMIN on a pin 12 (i.e. MIN) with the carrier voltage OSC. The output of the PWM comparator 216 has a duty cycle corresponding to the voltage VMIN on the pin 12.
Similarly, a PWM comparator 218 compares a voltage VTH on a pin 11 (i.e. TH) with the carrier voltage OSC. The output of the PWM comparator 218 has a duty cycle corresponding to the voltage VTH on the pin 11.
The control logic circuit 208 combines the output pulses of the PWM comparators 216 and 218 in order to generate the pulse signal S1. The larger duty cycle in the output pulses of the PWM comparators 216 and 218 becomes the duty cycle of the pulse signal S1. In other words, the voltage on the pin 12 is used to set the lower bound of the duty cycle (i.e. the minimum duty cycle) of the pulse signal S1.
A reference voltage source 214 generates a specific reference voltage VREF, and the specific reference voltage VREF is outputted to the external circuit via a pin 10 (i.e. REF). Resistors R11 and R12 divide the reference voltage VREF in order to generate a divided voltage on the input to the pin 12 (i.e. MIN). In other words, the voltage VMIN on the pin 12 can be set by the resistances of the external resistors R11 and R12. Thus, the minimum duty cycle of the pulse signal S1 can also be set.
The PWM input pin is arranged to input a PWM signal with the duty cycle corresponding to the target rotation number of the electric fan motor 6. In FIG. 1A, an input PWM signal is connected to the TH pin via an inverter 10.
In FIG. 1B, after an input PWM signal is inverted by an inverter 10, the inverted input PWM signal is smoothed by an RC filter 12, and is then inputted to the TH pin.
FIGS. 2A and 2B are timing diagrams illustrating the operating waveforms of the driving IC 200 in FIGS. 1A and 1B respectively.
Referring to FIG. 2A in conjunction with FIG. 1A, the operation of the driving IC 200 is described as follows.
The TH pin (i.e. pin 11) of the driving IC 200 of FIG. 1A is arranged to input the input pulse signal VTH, wherein the input pulse signal VTH corresponds to the inverted input PWM signal. The high voltage level for the pulse signal VTH is higher than the peak value of the carrier voltage generated by the internal oscillator, and the low voltage level for the pulse signal VTH is lower than the valley value of the carrier voltage generated by the internal oscillator. By comparing the carrier voltage with the pulse voltage VTH, the output pulse signal of the PWM comparator 218 has the same duty cycle as the duty cycle of the pulse voltage VTH.
FIG. 2A shows the waveforms of H−>H+, the output OUT1 having the first phase is changed, and the output OUT2 having the second phase is fixed at the low voltage level. The switching duty cycle of the output OUT1 is the same as VTH, and thus the switching duty cycle of the output OUT1 is the same as the duty cycle of the original input PWM signal. In addition, as VMIN equals to VREF and is higher than the peak value of the carrier voltage in this embodiment, the output of the PWM comparator 216 does not affect the output OUT1.
Therefore, when the PWM signal has a larger duty cycle, the torque (i.e. the rotation number) of the electric fan motor 6 is also higher.
In addition, referring to FIG. 2A in conjunction with FIG. 1B, the operation of the driving IC 200 is described as follows.
The TH pin (i.e. pin 11) of the driving IC 200 of FIG. 1B is arranged to input the DC voltage VTH after the DC voltage VTH is smoothed by a filter. When the output OUT1 equals the lower voltage of VMIN and VTH, the output OUT1 has the duty cycle corresponds to the comparison result of the carrier voltage.
Therefore, when the PWM signal has a larger duty cycle, the torque (i.e. the rotation number) of the electric fan motor 6 is also higher. In addition, the smallest torque, i.e. the minimum rotation number, can be set by the voltage VMIN.
Hence, according to the driving IC 200 in FIG. 1, the TH pin can be inputted by DC voltage, the TH pin can also be inputted by pulse signals. Therefore, the present embodiments provide a high flexibility of circuit components for the designer.